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Part 1: Design of VHDL or Verilog
This tutorial shows the construction of VHDL and Verilog code that blinks an LED at a specified frequency. Both VHDL and Verilog are shown, and you can choose which you want to learn first. Whenever design code is written the FPGA designer needs to ensure that it works the way that it was intended. Despite your best efforts, there will always be mistakes in your initial design. The best way to find these mistakes is in a simulation environment. This tutorial is broken up into 2 stages:
- Design of HDL
- Simulation of HDL
Part 1: Design of VHDL or Verilog. This tutorial shows the construction of VHDL and Verilog code that blinks an LED at a specified frequency. Both VHDL and Verilog are shown, and you can choose which you want to learn first. Whenever design code is written the FPGA designer needs to ensure that it works the way that it was intended. Visual Studio Code is an open source editor from Microsoft. VHDL-Tool makes its services available to VS Code through the Language Server Protocol. Find the plugin by searching for VHDL in the extensions sidebar, or go to the online marketplace. Explore VHDL Project Codes, VLSI Projects Topics, IEEE MATLAB Minor and Major Project Topics or Ideas, VHDL Based Research Mini Projects, Latest Synopsis, Abstract, Base Papers, Source Code, Thesis Ideas, PhD Dissertation for Electronics Science Students ECE, Reports in PDF, DOC and PPT for Final Year Engineering, Diploma, BSc, MSc, BTech and MTech Students for the year 2015 and 2016. Intelligent introduction to basic VHDL concepts, you should be able to quickly and e ciently create useful VHDL code. In this way, you will see VHDL as a valuable design, simulation and test tool rather than another batch of throw-away technical knowledge encountered in some forgotten class or lab. Lastly, VHDL is an extremely powerful tool. This Tool supports to Windows & Linux Platforms. The VHDL Programs runs on all Editions of Xilinx ISE Design Suite, including Xilinx ISE Webpack Edition, which is a Free Download Edition after completing successful Registration procedure with Xilinx (On Xilinx Website).
Both of these steps are crucial for successful FPGA development. Sometimes FPGA designers who are pressed for time will try to skip step two, the simulation of their code. However this is an extremely important step! Without proper simulation you will be forced to debug your code on hardware which can be a very difficult and time consuming endeavour.
Project Requirements:
Design HDL code that will blink an LED at a specified frequency of 100 Hz, 50 Hz, 10 Hz, or 1 Hz. For each of the blink frequencies, the LED will be set to 50% duty cycle (it will be on half the time). The LED frequency will be chosen via two switches which are inputs to the FPGA. There is an additional switch called LED_EN that needs to be ‘1’ to turn on the LED. The FPGA will be driven by a 25 MHz oscillator.
Let’s first draw the truth table for the frequency selector:
| Enable | Switch 1 | Switch 2 | LED Drive Frequency |
|---|---|---|---|
| 0 | - | - | (disabled) |
| 1 | 0 | 0 | 100 Hz |
| 1 | 0 | 1 | 50 Hz |
| 1 | 1 | 0 | 10 Hz |
| 1 | 1 | 1 | 1 Hz |
For this to work correctly there will be 4 inputs and 1 output. /amd-radeon-hd-7340-graphics-driver-download.html. The signals will be:
| Signal Name | Direction | Description |
|---|---|---|
| i_clock | Input | 25 MHz Clock |
| i_enable | Input | The Enable Switch (Logic 0 = No LED Drive) |
| i_switch_1 | Input | Switch 1 in the Truth Table above |
| i_switch_2 | Input | Switch 2 in the Truth Table above |
| o_led_drive | Output | The signal that drives the LED |
For the design there are four counter processes that run concurrently. This means that they are all running at the exact same time. Their job is to keep track of the number of clock pulses seen for each of the different frequencies. Even if the switches are not selecting that particular frequency, the counters are still running! This is the beauty of Hardware Design and concurrency. Everything runs all the time! It can be challenging to understand this initially, but it is the core concept that you need to master.
The switches only serve to select which output to use. They create what is known as a multiplexer. A multiplexer or mux for short is a selector that will select one of a number of inputs to propagate or pass to the output. It is a combinatorial piece of logic, meaning that it does not require a clock to operate. Below is a block diagram of the design. Spend some time thinking about how you might implement this design. Try writing the code yourself. The way that I chose to do can be found below.
VHDL code for the design, tutorial_led_blink.vhd:
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Verilog code for the design, tutorial_led_blink.v:
Next Step: Simulating this design in VHDL or Verilog!
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